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d a t a sh eet product speci?cation supersedes data of 2002 aug 15 2003 may 14 integrated circuits TZA3052AHW 2.5 and 2.7 gbits/s fibre optic receiver
2003 may 14 2 philips semiconductors product speci?cation 2.5 and 2.7 gbits/s ?bre optic receiver TZA3052AHW features single 3.3 v power supply supports sdh/sonet bit rates at 2488.32 and 2666.06 mbits/s (stm16/oc48 and stm16/oc48 + fec) with 19.44 mhz reference frequency limiting input with 12 mv sensitivity received signal strength indicator (rssi) loss of signal (los) indicator with threshold adjust frequency lock indicator itu-t compliant jitter tolerance 1:16 demultiplexing ratio low voltage positive emitter coupled logic (lvpecl) demultiplexer outputs frame detector for sdh/sonet frames parity bit generation recovered data and clock loop mode outputs loop mode inputs on demultiplexer temperature alarm pin compatible with tza3012ahw. applications sdh/sonet optical transmission system with bit rates of 2.5 and 2.7 gbits/s physical interface ic in receive channels transponder applications dense wavelength division multiplexing (dwdm) systems. general description the TZA3052AHW is a fully integrated optical network receiver containing a limiter, data and clock recovery (dcr) and 1:16 demultiplexer. the ic operates at the bit rates 2.5 and 2.7 gbits/s with one single reference frequency. the receiver supports loop modes with serial clock and data inputs and outputs. ordering information type number package name description version TZA3052AHW htqfp100 plastic, heatsink thin quad ?at package; 100 leads; body 14 14 1.0 mm sot638-1
2003 may 14 3 philips semiconductors product speci?cation 2.5 and 2.7 gbits/s ?bre optic receiver TZA3052AHW this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... block diagram l l pagewidth rssi los dloop enlinq dloopq cloopq enba cloop 13 33 6 7 9 10 5878884859152 34 27 2 2 390 32 dmx 1 : 16 parity generator d00 to d15 parity parityq d00q to d15q poclk inwindow enloutq winsize crefq prscloq cref prsclo i.c. rref inq in losth temperature alarm TZA3052AHW rssi los lim phase detector lpf frequency window detector 28, 29 14 dr 22 16 2 2 2 2 38 41 42 36 37 39 16 c c d d 44, 46, 48, 53 55, 57, 59, 61, 64, 66, 68, 70 72, 77, 79, 81 poclkq fp fpq 94 95 cout coutq 97 98 92 dout doutq tempal mgu704 16 45, 47, 49, 54 56, 58, 60, 62, 65, 67, 69, 71 73, 78, 80, 82 v cca 8, 11, 15, 18 11 n.c. 4, 12, 16, 17, 19, 20, 21, 23, 24, 30, 31 4 v ccd 1, 35, 40, 43, 51 75, 76, 83, 86, 89, 93, 96, 99 v cco 25 v dd 26, 50, 63, 74, 100 v ee 13 lim = limiting amplifier. rssi = receiving signal strength indicator. los = loss of signal detector. lpf = low-pass filter. dmx = demultiplexer. fig.1 simplified block diagram.
2003 may 14 4 philips semiconductors product speci?cation 2.5 and 2.7 gbits/s ?bre optic receiver TZA3052AHW pinning symbol pin description v ee die pad common ground plane v ccd 1 supply voltage (digital part) prsclo 2 prescaler output prscloq 3 prescaler output inverted n.c. 4 not connected los 5 los output of input channel rssi 6 received signal strength indicator output of input channel losth 7 los threshold input for input channel v cca 8 supply voltage (analog part) in 9 channel input inq 10 channel input inverted v cca 11 supply voltage (analog part) n.c. 12 not connected winsize 13 wide and narrow frequency detect window select rref 14 reference resistor input v cca 15 supply voltage (analog part) n.c. 16 not connected n.c. 17 not connected v cca 18 supply voltage (analog part) n.c. 19 not connected n.c. 20 not connected n.c. 21 not connected dr 22 data rate selection input n.c. 23 not connected n.c. 24 not connected v dd 25 supply voltage (digital) v ee 26 ground inwindow 27 frequency window detector output i.c. 28 internally connected i.c. 29 internally connected n.c. 30 not connected n.c. 31 not connected v cco 32 supply voltage (clock generator) cref 33 reference clock input crefq 34 reference clock input inverted v ccd 35 supply voltage (digital part) fp 36 frame pulse output fpq 37 frame pulse output inverted parity 38 parity output parityq 39 parity output inverted v ccd 40 supply voltage (digital part) poclk 41 parallel clock output poclkq 42 parallel clock output inverted v ccd 43 supply voltage (digital part) d00 44 parallel data output 00 d00q 45 parallel data output 00 inverted d01 46 parallel data output 01 d01q 47 parallel data output 01 inverted d02 48 parallel data output 02 d02q 49 parallel data output 02 inverted v ee 50 ground v ccd 51 supply voltage (digital part) enba 52 byte alignment enable input d03 53 parallel data output 03 d03q 54 parallel data output 03 inverted d04 55 parallel data output 04 d04q 56 parallel data output 04 inverted d05 57 parallel data output 05 d05q 58 parallel data output 05 inverted d06 59 parallel data output 06 d06q 60 parallel data output 06 inverted d07 61 parallel data output 07 d07q 62 parallel data output 07 inverted v ee 63 ground d08 64 parallel data output 08 d08q 65 parallel data output 08 inverted d09 66 parallel data output 09 d09q 67 parallel data output 09 inverted d10 68 parallel data output 10 d10q 69 parallel data output 10 inverted d11 70 parallel data output 11 d11q 71 parallel data output 11 inverted d12 72 parallel data output 12 d12q 73 parallel data output 12 inverted v ee 74 ground v ccd 75 supply voltage (digital part) symbol pin description
2003 may 14 5 philips semiconductors product speci?cation 2.5 and 2.7 gbits/s ?bre optic receiver TZA3052AHW v ccd 76 supply voltage (digital part) d13 77 parallel data output 13 d13q 78 parallel data output 13 inverted d14 79 parallel data output 14 d14q 80 parallel data output 14 inverted d15 81 parallel data output 15 d15q 82 parallel data output 15 inverted v ccd 83 supply voltage (digital part) cloop 84 loop mode clock input cloopq 85 loop mode clock input inverted v ccd 86 supply voltage (digital part) dloop 87 loop mode data input dloopq 88 loop mode data input inverted v ccd 89 supply voltage (digital part) symbol pin description enloutq 90 line loop back enable input (active low) enlinq 91 diagnostic loop back enable input (active low) tempal 92 temperature alarm output v ccd 93 supply voltage (digital part) cout 94 recovered clock output coutq 95 recovered clock output inverted v ccd 96 supply voltage (digital part) dout 97 recovered data output doutq 98 recovered data output inverted v ccd 99 supply voltage (digital part) v ee 100 ground symbol pin description
2003 may 14 6 philips semiconductors product speci?cation 2.5 and 2.7 gbits/s ?bre optic receiver TZA3052AHW handbook, full pagewidth 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 v dd n.c. n.c. dr n.c. n.c. n.c. v cca n.c. n.c. v cca rref winsize n.c. v cca inq in v cca losth rssi los n.c. prscloq prsclo v ccd v ccd enba d03 d03q d04 d04q d05 d05q d06 d06q d07 d07q v ee d08 d08q d09 d09q d10 d10q d11 d11q d12 d12q v ee v ccd 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 v ee v ccd doutq dout v ccd coutq cout v ccd tempal enlinq enloutq v ccd dloopq dloop v ccd cloopq cloop v ccd d15q d15 d14q d14 d13q d13 v ccd v ee inwindow i.c. i.c. n.c. n.c. v cco cref crefq v ccd fp fpq parity parityq v ccd poclk poclkq v ccd d00 d00q d01 d01q d02 d02q v ee 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 mgu703 TZA3052AHW fig.2 pin configuration.
2003 may 14 7 philips semiconductors product speci?cation 2.5 and 2.7 gbits/s ?bre optic receiver TZA3052AHW functional description the TZA3052AHW receives data from an incoming bit stream with a bit rate of 2.5 or 2.7 gbits/s. a dcr section synchronizes the internal clock generator with the incoming data. the recovered serial data and clock are demultiplexed with a ratio of 1:16. con?guring the TZA3052AHW using pin dr the ic features two types of bit rates with the use of a 19.44 mhz reference clock connected to pins cref and crefq. pin dr acts as a standard cmos input that selects one of the desired bit rates as given in table 1. table 1 truth table for pin dr limiting ampli?er the incoming bitstream is amplified by the limiting amplifier (see fig.3). received signal strength indicator (rssi) the signal strength at the input is measured with a logarithmic detector and presented at pin rssi. the rssi reading has a sensitivity of typically 17 mv/db for a v i(p-p) range of 5 to 500 mv (see fig.4). v rssi can be calculated using the following formula: pin dr protocol bit rate (mbits/s) low stm16/oc48 2488.32 high stm16 + fec 2667.00 handbook, halfpage mdb385 50 w in inq 50 w v ee v cca fig.3 limiter input termination configuration. v rssi v rssi 32mv () s rssi 20log v i(p-p) 32 mv ---------------- - + = handbook, full pagewidth mbl555 0 5 0.3 0.6 0.9 1.2 v rssi (v) s rssi 10 32 10 2 10 3 500 300 v i(p-p) (mv) fig.4 v rssi as a function of v i(p-p) .
2003 may 14 8 philips semiconductors product speci?cation 2.5 and 2.7 gbits/s ?bre optic receiver TZA3052AHW loss of signal (los) indicator besides the analog rssi output, a digital los indication is present on the TZA3052AHW. the rssi level is internally compared with a los threshold, which can be set by an external resistor (pin losth). if the received signal strength is below the threshold value, pin los will be high. a hysteresis of 2.5 db is applied in the comparator. setting losth reference level by external resistor the reference voltage level on pin losth can be set by connecting an external resistor (r2) between the relevant pin and ground (see fig.5). the voltage on the pin is determined by the ratio of resistors r2 and r1. for resistor r1 a value of 10 to 20 k w is recommended, yielding a current of 120 to 60 m a. the losth voltage equals voltage v ref represents a temperature stabilized, accurate reference voltage of 1.2 v. the minimum threshold level corresponds to 0 v and the maximum to 1.2 v. hence, the value of r2 may not be higher than r1. the accuracy of the losth voltage depends mainly on the matching of the two external resistors. instead of using resistors (r1 and r2) to set the los threshold, an accurate external voltage source can be used. if no resistor is connected to pin losth, or an external voltage higher than 2 3 v cc is applied to the pin, the los detection circuit (including the rssi reading) is automatically switched off to reduce power dissipation. data and clock recovery (dcr) the TZA3052AHW recovers the clock and data contents from the incoming bit stream (see fig.6). the dcr uses a combined frequency and phase locking scheme, providing reliable and quick data acquisition. initially, at power-up, coarse adjustment of the free running vco frequency is required. this is achieved by the frequency window detector (fwd) circuit. the fwd is a conventional frequency locked pll. the fwd checks the vco frequency, which has to be within a 1000 ppm (parts per million) window around the desired frequency. the fwd then compares the divided vco frequency (also available on pins prsclo and prscloq with the reference frequency of 19.44 mhz on pins cref and crefq. if the vco frequency is found to be outside this window, the fwd disables the data phase detector (dpd) and forces the vco to a frequency within the window. as soon as the in window condition occurs, which is visible on pin inwindow, the dpd starts acquiring lock on the incoming bit stream. since the vco frequency is very close to the expected bit rate, the phase acquisition will be almost instantaneous, resulting in quick phase lock to the incoming data stream. although the vco is now locked to the incoming bit stream, the fwd is still supervising the vco frequency and takes over control if the vco drifts outside the predefined frequency window. this might occur during a loss of signal situation. due to the fwd, the vco frequency is always close to the required bit rate, enabling rapid phase acquisition if the lost input signal state returns. due to the loose coupling of 1000 ppm, the reference frequency does not need to be highly accurate or stable. any crystal-based oscillator that generates a reasonably accurate frequency (e.g. within 100 ppm) can be used. r2 r1 ------- - v ref rssi los compare losth 1.2 v v ref rref v ee los mgu705 v cca ground r2 r1 10 k w i fig.5 setting the losth reference level by external resistors.
2003 may 14 9 philips semiconductors product speci?cation 2.5 and 2.7 gbits/s ?bre optic receiver TZA3052AHW handbook, full pagewidth + data phase detector up recovered data data in cref(q) (19.44 mhz) dr prsclo(q) mgu706 recovered clock to demultiplexer limiting amplifier prescaler output reference input 2488.32 or 2666.06 mbits/s down charge pump loop filter frequency window detector up down voltage controlled oscillator (vco) charge pump fig.6 block diagram of data and clock recovery. prescaler outputs prescaler output pins prsclo and prscloq are always a measure of the internal frequency of the dcr. it is the vco frequency divided by the selected division factor. it can be used as an accurate reference for another pll, since it corresponds to the recovered data rate. programming the fwd the default width of the window for frequency acquisition is 1000 ppm around the desired bit rate. a window width of 0 ppm can be set using pin winsize. this effectively removes the dead zone from the fwd, rendering the fwd into a classical pll. the vco will be locked directly to the reference signal instead of to the incoming bit stream. table 2 truth table for pin winsize accurate clock generation during loss of signal a zero window size is especially interesting in the absence of input data, since the frequency of the recovered clock will be equal to the reference frequency including its tolerance. the accuracy of the reference frequency needs to be better than 20 ppm if the application is to comply with itu-t recommendations. inwindow signal the status of the fwd circuit is reflected in the state of pin inwindow: high for an in window situation and low whenever the vco is outside the defined frequency window. jitter performance the TZA3052AHW has been optimized for best jitter tolerance performance. for the sdh/sonet stm16/oc48 bit rate, the jitter tolerance exceeds compliance with itu-t standard g.958. pin winsize frequency window low 0 ppm high 1000 ppm
2003 may 14 10 philips semiconductors product speci?cation 2.5 and 2.7 gbits/s ?bre optic receiver TZA3052AHW demultiplexer the demultiplexer converts the serial input bit stream to parallel format (1:16). the output data is available on a standard lvpecl output driver type (see fig.10). as well as the deserializing function, the demultiplexer comprises a parity calculator and a frame header detection circuit. the calculated parity (even) is output at pins parity and parityq, whereas occurrence of the frame header pattern in the data stream results in a 1 clock cycle wide pulse on pins fp and fpq. frame detection byte alignment is enabled if the enable byte alignment (enba) input is high. whenever a 32-bit sequence matches the frame header pattern, the incoming data is formatted into logical bytes or words and a frame pulse is generated on differential outputs fp and fpq. the frame header pattern is f6f62828h, corresponding to the middle section of the standard sdh/sonet frame header (the last two a1 bytes plus the first two a2 bytes). figure 7 shows a typical sdh/sonet reframe sequence involving byte alignment. frame and byte boundary detection is enabled on the rising edge of enba and remains enabled while enba is high. boundaries are recognized on receipt of the second a2 byte and fp goes high for one poclk cycle. the first two a2 bytes in the frame header are the first data word to be reported with the correct alignment on the outgoing data bus (d00 to d15). when interfacing with a section terminating device, enba must remain high for a full frame after the initial frame pulse. this is to allow the section terminating device to verify internally that frame and byte alignment are correct (see fig.8). byte boundary detection is disabled on the first fp pulse after enba has gone low. figure 9 shows frame and byte boundary detection activated on the rising edge of enba, and deactivated by the first fp pulse after enba has gone low. if enba is low, no active alignment takes place. however, if the framing pattern happens to occur in the formatted data, a frame pulse will still be output on pins fp and fpq. handbook, full pagewidth mgu707 valid data invalid data serial clock enba serial data d00 to d15 (1:16) poclk (1:16) fp (1:16) a1 a1 a2 28 28 1 : 16 a2 a1 a2 a2 32 bits fig.7 frame and byte detection in sdh/sonet application.
2003 may 14 11 philips semiconductors product speci?cation 2.5 and 2.7 gbits/s ?bre optic receiver TZA3052AHW handbook, halfpage mgu340 enba fp boundary detection enabled fig.8 enba timing with section terminating device. handbook, halfpage mgu341 enba fp boundary detection enabled fig.9 alternate enba timing. parity generation output pins parity and parityq provide the even parity of the byte/word that is currently available on the parallel bus. loop mode i/os the ic can be used in a diagnostic loop back mode by setting pin enlinq to low. in this case, the demultiplexer will select inputs dloop and dloopq, cloop and cloopq instead of taking the input from the dcr. the line loop back mode is activated by setting pin enloutq to low. now, the recovered clock and serial data will be available at output pins dout and doutq and cout and coutq. rf i/os the rf cml outputs have an amplitude of 80 mv (p-p) single-ended. the termination scheme is ac coupled (see fig.11). cmos control inputs most cmos control inputs have an internal pull-up resistor. if the input is required to be high, it can be left open-circuit. only the low state needs to be actively forced. this applies to pins winsize, enba, enloutq, enlinq and dr. power supply connections four separate supply domains (v dd , v ccd , v cco and v cca ) provide isolation between the various functional blocks. each supply domain should be connected to a common v cc via separate filters. all supply pins, including the exposed die pad, must be connected . the die pad should be connected with the lowest inductance possible. since the die pad is also used as the main ground return of the chip, the connection should have a low dc impedance as well. the voltage supply levels should be in accordance with the values specified in chapter characteristics. all external components should be surface mounted devices, preferably of size 0603 or smaller. the components must be mounted as closely to the ic as possible. temperature alarm the TZA3052AHW features a temperature alarm. the temperature alarm switches the open-drain output of pin tempal to low at a junction temperature above 130 c.
2003 may 14 12 philips semiconductors product speci?cation 2.5 and 2.7 gbits/s ?bre optic receiver TZA3052AHW limiting values in accordance with the absolute maximum rating system (iec 60134). thermal characteristics notes 1. in compliance with jedec standards jesd51-5 and jesd51-7. 2. four-layer printed-circuit board (pcb) in still air with 36 plated vias connected with the heatsink and the second and fourth layers of the pcb. symbol parameter min. max. unit v cca , v ccd , v cco , v dd supply voltages - 0.5 + 3.6 v v n dc voltage on pins d00 and d00q to d15 and d15q, poclk and poclkq, fp and fpq, parity and parityq, prsclo and prscloq v cc - 2.5 v cc + 0.5 v pins losth and rref - 0.5 v cc + 0.5 v pin rssi - 0.5 v cc + 0.5 v pins winsize, dr, enba, enloutq and enlinq - 0.5 v cc + 0.5 v pins los and inwindow - 0.5 v cc + 0.5 v pin tempal - 0.5 v cc + 0.5 v i n input current on pins in and inq - 30 + 30 ma pins cref and crefq, cloop and cloopq, dloop and dloopq - 20 + 20 ma pin tempal - 2 + 2ma t amb ambient temperature - 40 + 85 c t j junction temperature + 125 c t stg storage temperature - 65 + 150 c symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient notes 1 and 2 16 k/w
2003 may 14 13 philips semiconductors product speci?cation 2.5 and 2.7 gbits/s ?bre optic receiver TZA3052AHW characteristics t amb = - 40 to + 85 c; v cc = 3.14 to 3.47 v; r th(j-a) 16 k/w; all characteristics are specified for the default setting (note 1); all voltages are referenced to ground; positive currents flow into the device; unless otherwise specified. symbol parameter conditions min. typ. max. unit general i cca analog supply current 15 20 27 ma i ccd digital supply current 270 350 450 ma i cco oscillator supply current 20 25 33 ma i dd digital supply current 0 0 1 ma i cc(tot) total supply current 305 395 511 ma p tot total power dissipation 0.96 1.3 1.77 w cmos input; pins dr, winsize, enba, enloutq and enlinq v il low-level input voltage -- 0.2v cc v v ih high-level input voltage 0.8v cc -- v i il low-level input current v il =0v - 200 -m a i ih high-level input current v ih =v cc -- 10 m a cmos output; pins los and inwindow v ol low-level output voltage i ol =1ma 0 - 0.2 v v oh high-level output voltage i oh = - 0.5 ma v cc - 0.2 - v cc v open-drain output; pin tempal v ol low-level output voltage i ol =1ma 0 - 0.2 v i oh high-level output current v oh =v cc -- 10 m a serial output; pins cout, coutq, dout and doutq v o(p-p) output voltage swing (peak-to-peak value) single-ended with 50 w external load; enloutq = low; see fig.11 50 80 110 mv z o output impedance single-ended to v cc 80 100 120 w t r rise time 20% to 80% - 100 - ps t f fall time 80% to 20% - 100 - ps t d-c data-to-clock delay between differential crossovers of cout, coutq, dout and doutq; see fig.12 80 140 200 ps d duty cycle signals cout and coutq between differential crossovers 40 50 60 % serial input; pins cloop, cloopq, dloop and dloopq v i(p-p) input voltage (peak-to-peak value) single-ended 50 - 1000 mv v i dc input voltage v cc - 1 - v cc + 0.25 v z i input impedance single-ended to v cc 40 50 60 w t d clock delay see fig.13 260 340 400 ps
2003 may 14 14 philips semiconductors product speci?cation 2.5 and 2.7 gbits/s ?bre optic receiver TZA3052AHW t su set-up, see fig.13 15 30 60 ps t h hold time see fig.13 15 30 60 ps d duty cycle signals cloop and cloopq between differential crossovers 40 50 60 % lvpecl mode parallel output; pins d00 and d00q to d15 and d15q, fp, fpq, parity, parityq, poclk, poclkq, prsclo and prscloq v oh high-level output voltage 50 w termination to v cc - 2 v; see fig.10 v cc - 1.2 v cc - 1.0 v cc - 0.9 v v ol low-level output voltage 50 w termination to v cc - 2 v; see fig.10 v cc - 2.0 v cc - 1.9 v cc - 1.7 v t r rise time 20% to 80% 300 350 400 ps t f fall time 80% to 20% 300 350 400 ps timing parallel output; pins d00 and d00q to d15 and d15q, fp, fpq, parity, parityq, poclk, poclkq, prsclo and prscloq t d-c data-to-clock delay between differential crossovers of d00 to d15 and poclk see fig.14; note 2 100 100 250 ps d duty cycle poclk 40 50 60 % skew channel to channel skew between channels (d00 and dn) note 2 -- 200 ps reference; pin rref v ref reference voltage 10 to 20 k w resistor to v ee 1.17 1.21 1.26 v rf input; pins in and inq v i(p-p) input voltage swing (peak-to-peak value) single-ended; note 3 12 - 500 mv z i input impedance differential 80 100 120 w a iso between channel isolation - 60 - db received signal strength indicator (rssi) v i(p-p) input voltage swing (peak-to-peak value) single-ended 5 - 500 mv s rssi rssi sensitivity see fig.4 15 17 20 mv/db v rssi rssi output voltage v i(p-p) =32mv; prbs (2 31 - 1) 580 680 780 mv d v o(rssi) output voltage variation input 2.5 and 2.7 gbits/s; prbs (2 31 - 1); v cc = 3.14 to 3.47 v; d t amb = 120 c - 50 -+ 50 mv output; pin rssi z o output impedance - 110 w i o(source) output source current -- 1ma symbol parameter conditions min. typ. max. unit
2003 may 14 15 philips semiconductors product speci?cation 2.5 and 2.7 gbits/s ?bre optic receiver TZA3052AHW notes 1. default settings: dr = low (stm16/oc48); winsize = high (1000 ppm); enba = high (automatic byte alignment); enloutq = high (dout, cout disabled); enlinq = high (dloop, cloop disabled); cref and crefq = 19.44 mhz; d00 and d00q to d15 and d15q, fp, fpq, parity, parityq, poclk, poclkq, prsclo and prscloq are not connected. 2. with 50% duty cycle. 3. the rf input is protected against a differential overvoltage; the maximum input current is 30 ma. it is assumed that both inputs carry a complementary signal of the specified peak-to-peak value. 4. at t amb = - 40 to 0 c the minimum value is 0.25 ui at f = 1 mhz and 20 mhz. i o(sink) output sink current -- 0.4 ma los detector hys hysteresis 2 3 4 db t a assert time d v i(p-p) =3db -- 5 m s t d de-assert time d v i(p-p) =3db -- 5 m s reference frequency input; pins cref and crefq v i(p-p) input voltage (peak-to-peak value) single-ended 50 - 1000 mv v i dc input voltage v cc - 1 - v cc + 0.25 v z i input impedance single-ended to v cc 40 50 60 w d f cref reference clock frequency accuracy sdh/sonet operation, f cref = 19.44 mhz - 20 -+ 20 ppm pll characteristics t acq acquisition time -- 200 m s t acq(pc) acquisition time at power cycle -- 10 ms tdr transitionless data run - 1000 - bits jitter tolerance j tol(p-p) jitter tolerance (peak-to-peak value) stm16/oc48 mode (itu-t g.958); prbs (2 23 - 1); note 4 f = 100 khz 3 10 - ui f = 1 mhz 0.3 1 - ui f = 20 mhz 0.3 0.5 - ui symbol parameter conditions min. typ. max. unit
2003 may 14 16 philips semiconductors product speci?cation 2.5 and 2.7 gbits/s ?bre optic receiver TZA3052AHW handbook, full pagewidth mbl562 v cc out transmission lines optional ac coupling to high- impedance input 50 w 50 w 2 v v term 50 w 50 w outq i swing in swing control on-chip off-chip fig.10 standard pecl mode. handbook, full pagewidth mbl563 v cc v bias out transmission lines recommended for serial outputs to high- impedance input 50 w 50 w 100 w 100 w 50 w 100 w 100 w 50 w outq i swing in swing control on-chip off-chip 120 w fig.11 cml ac coupled mode.
2003 may 14 17 philips semiconductors product speci?cation 2.5 and 2.7 gbits/s ?bre optic receiver TZA3052AHW handbook, full pagewidth mgu345 t d-c cout dout fig.12 loop mode output timing. the timing is measured from the crossover point of the clock output signal to the crossover point of the data output (all signa ls are differential). mbl554 handbook, halfpage cloop dloop t d t su t h fig.13 loop mode input timing. the timing is measured from the crossover point of the clock input signal to the crossover point of the data input. handbook, full pagewidth mgu343 poclk d00 to d15, fp, parity t d-c fig.14 parallel bus output timing. the timing is measured from the crossover point of the clock output signal to the crossover point of the data output (all signa ls are differential).
2003 may 14 18 philips semiconductors product speci?cation 2.5 and 2.7 gbits/s ?bre optic receiver TZA3052AHW package outline unit a max. a 1 a 2 a 3 b p h d h e l p z d (1) z e (1) cely w v q references outline version european projection issue date iec jedec jeita mm 1.2 0.15 0.05 1.05 0.95 0.25 0.27 0.17 0.20 0.09 14.1 13.9 0.5 16.15 15.85 1.15 0.85 7 0 0.08 0.08 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot638-1 01-03-30 03-04-07 d (1) e (1) 14.1 13.9 16.15 15.85 d h e h 7.1 6.1 7.1 6.1 1.15 0.85 b p b p e q e a 1 a l p detail x l (a 3 ) b 25 h d h e a 2 v m b d z d a c z e e v m a x 1 100 76 75 51 50 26 y pin 1 index w m w m 0 10 mm scale htqfp100: plastic thermal enhanced thin quad flat package; 100 leads; body 14 x 14 x 1 mm; exposed die pad sot638-1 d h e h exposed die pad side
2003 may 14 19 philips semiconductors product speci?cation 2.5 and 2.7 gbits/s ?bre optic receiver TZA3052AHW soldering introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 220 c for thick/large packages, and below 235 c for small/thin packages. wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2003 may 14 20 philips semiconductors product speci?cation 2.5 and 2.7 gbits/s ?bre optic receiver TZA3052AHW suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales office. 2. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 3. these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 5. wave soldering is suitable for lqfp, tqfp and qfp packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. wave soldering is suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package (1) soldering method wave reflow (2) bga, lbga, lfbga, sqfp, tfbga, vfbga not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, hvson, sms not suitable (3) suitable plcc (4) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (4)(5) suitable ssop, tssop, vso not recommended (6) suitable
2003 may 14 21 philips semiconductors product speci?cation 2.5 and 2.7 gbits/s ?bre optic receiver TZA3052AHW data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2003 may 14 22 philips semiconductors product speci?cation 2.5 and 2.7 gbits/s ?bre optic receiver TZA3052AHW notes
2003 may 14 23 philips semiconductors product speci?cation 2.5 and 2.7 gbits/s ?bre optic receiver TZA3052AHW notes
? koninklijke philips electronics n.v. 2003 sca75 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands 403510/02/pp 24 date of release: 2003 may 14 document order number: 9397 750 10313

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